In recent years, the size reduction and performance enhancement of electronic apparatuses have been rapidly in progress. In addition, there has been significant progress in increasing transmission speed (an increased frequency exceeding 1 GHz) and reducing driving voltage, as typically seen in high-speed transmission systems, such as USB2.0, S-ATA2, and HDMI. On the other hand, the withstand voltage of electronic components used in electronic apparatuses decreases with the size reduction of electronic apparatuses and reduced driving voltage therefor. Therefore, the protection of electronic components from overvoltage typified by electrostatic pulses generated when a human body comes into contact with a terminal of an electronic apparatus has become an important technical problem.
Conventionally, in order to protect electronic components from such electrostatic pulses, a method of providing a stacked varistor between the ground and a line to be subjected to static electricity has generally been used. However, the varistor generally has large electrostatic capacitance, and therefore, when it is used in a high-speed transmission system, it becomes a factor in degrading signal quality. Therefore, the development of an ESD protection device having small electrostatic capacitance, that is applicable to high-speed transmission systems, has been required.
As an ESD protection device having low electrostatic capacitance, one in which an electrostatic protection material is filled between electrodes arranged away from and opposite each other has been proposed. An ESD protection device of this type in which what is called gap type electrodes are mounted has the advantages of large insulation resistance, small electrostatic capacitance, and good responsivity. On the other hand, a problem of the ESD protection device is that breakage (melting, deformation, and the like) occurs easily in the electrodes and their periphery (hereinafter simply referred to as the “electrode periphery”) due to heat and stress generated by discharge.
As a technique for inhibiting the breakage of the electrode periphery, for example, Patent Document 1 describes a multilayer chip varistor in which a ceramic body (electrostatic protection material) made of a protection material and having small holes, for inhibiting transient surge voltage and electrostatic shock, is located between opposite electrodes. In this technique, as the protection material, composite particles in which surfaces of semi-conductive particles or conductive particles having a particle size larger than 0.1 microns are coated with a layer of inorganic glass are used, and the above-described small holes are formed between these composite particles (see FIG. 2 in Patent Document 1).
In addition, Patent Document 2 describes an ESD protection device including discharge electrodes arranged away from and opposite each other, a cavity section provided above the discharge electrodes, and a mixing section (electrostatic protection material) located below and adjacent to the discharge electrodes.